The invention relates generally to a patterning method of a semiconductor device and, more particularly, to a patterning method of a semiconductor device, wherein an abrupt winding of a layer, which becomes a target, is eased by modifying an exposure mask pattern, thereby subsequently forming a uniform layer.
A semiconductor device includes a cell area for storing data and a peripheral (“peri”) area. An area where the cell and peri areas are formed on a wafer is called a die. A plurality of such dies is formed on a sheet of the wafer. The dies are isolated from each other with scribe lanes intervening therebetween.
As described above, elements having different pattern sizes are formed on a semiconductor substrate. In particular, as semiconductor devices have become more highly integrated, the width of a pattern and a gap between the patterns have decreased, so that the step of the pattern is gradually increased. Particularly, it may become difficult to form a subsequent layer since the pattern may have a wide open area. More specifically, overlay vernier patterns for alignment in the fabrication process of a semiconductor device are contained within the scribe lane area. The overlay vernier patterns have a gap wider than those of memory cell patterns of the cell area. If a layer is formed in a subsequent process, the formed layer may become weak at corner areas due to sharp pattern windings of the overlay vernier patterns. This is described in more detail with reference to photographs of FIG. 1.
FIGS. 1A and 1B are photographs showing a conventional overlay vernier pattern.
FIG. 1A shows a sectional view of an overlay vernier pattern of a semiconductor device wherein a corner of an overlay vernier pattern 102 has a sharp pattern winding 100. From FIG. 1A, it can be seen that, when a subsequent layer 104 is formed on the overlay vernier pattern 102 having the sharp pattern winding 100, a defects occurs at the area where the sharp pattern winding 100 is generated. This is because, since the subsequent layer 104 is weakly formed in the sharp pattern winding (100) area, a part of the overlay vernier pattern 102 can be exposed in a subsequent etch process, resulting in a defect.
FIG. 1B is a plan view of the overlay vernier pattern having defects 100 as in FIG. 1A. (The overlay vernier pattern is a pattern for alignment in the fabrication process of a semiconductor device.) If the defects 100 are generated as in FIG. 1B, it may become very difficult to perform accurate alignment, resulting in a low yield.